Platform/Sgi: Add MPAM ACPI table for RD-N2-Cfg1

Add MPAM ACPI table based on MPAM ACPI 1.0 specification for RD-N2-Cfg1
reference design platform. OS would query this table to understand
about the type and details of the MSCs supported by the platform.

RD-N2-Cfg1 platform supports 8 SLC slices. Each of these slices have
individual MPAM MSC controls and register set. PPTT defines this group
of cache slices as one single cache, tagged with a unique cache ID. All
the MSCs would in-turn refer to this unique cache ID given in the PPTT
ACPI description.

As the macro SGI_REMOTE_CHIP_MEM_OFFSET is used by
RD_MPAM_MSC_NODE_INIT macro, add a reference to
PcdMaxAddressBitsPerChip PCD.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8e5111b51225abae4ee8a896c3817c8bb88667a7

Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Mpam.aslc

+/** @file
+
+  Memory System Resource Partitioning and Monitoring (MPAM) for RD-N2-Cfg1
+  platform
+
+  MPAM ACPI description for the MSCs (Memory system components) for RD-N2-Cfg1
+  reference design platform is contained within this file. RD-N2-Cfg1 supports 8
+  HNF slices, each holding 1 MB of SLC cache. Each of these SLC cache slices in
+  turn holds MPAM MSC controls and associated register files. MPAM has separate
+  secure and non-secure register spaces. Since non-secure OS is generally
+  concerned with the non-secure register space, all of the non-secure nodes
+  should be described within the MPAM ACPI table
+
+  Copyright (c) 2022, Arm Limited. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+    - MPAM 1.0, Memory System Resource Partitioning and Monitoring
+**/
+
+#include <IndustryStandard/Mpam.h>
+#include <Library/AcpiLib.h>
+#include "SgiAcpiHeader.h"
+
+/*
+ * Macros for RD-N2-Cfg1's MPAM table
+ */
+#define MPAM_MSC_COUNT                                (8)
+#define MPAM_MMIO_SIZE                                (0x1000)
+#define RESOURCES_PER_MSC                             (0x01)
+#define FUNCTIONAL_DEPENDENCY_PER_RESOURCE            (0x0)
+
+typedef EFI_ACPI_DESCRIPTION_HEADER
+  EFI_ACPI_6_4_MPAM_HEADER;
+
+///
+/// MPAM MSC type. For RD-N2-Cfg1, MPAM MSC structure doesn't have any
+/// functional dependency list.
+///
+typedef struct {
+  MPAM_MSC_NODE            Header;
+  MPAM_MSC_RESOURCE        Resource;
+} MPAM_MSC;
+
+///
+/// MPAM ACPI Table
+///
+typedef struct {
+  EFI_ACPI_6_4_MPAM_HEADER Header;
+  MPAM_MSC                 Node[MPAM_MSC_COUNT];
+} EFI_ACPI_6_4_MEMORY_SYSTEM_RESOURCE_PARTITIONING_MONITORING_TABLE;
+
+
+STATIC EFI_ACPI_6_4_MEMORY_SYSTEM_RESOURCE_PARTITIONING_MONITORING_TABLE Mpam =
+{
+
+  /* EFI_ACPI_6_4_MPAM_HEADER */
+  ARM_ACPI_HEADER (
+    EFI_ACPI_6_4_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_SIGNATURE,
+    EFI_ACPI_6_4_MEMORY_SYSTEM_RESOURCE_PARTITIONING_MONITORING_TABLE,
+    EFI_ACPI_6_4_MEMORY_SYSTEM_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_REVISION
+  ),
+  {
+    /* MPAM_MSC_NODE 1 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x1, 0x141601000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+
+    /* MPAM_MSC_NODE 2 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x2, 0x141641000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+
+    /* MPAM_MSC_NODE 3 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x3, 0x141a01000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+
+    /* MPAM_MSC_NODE 4 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x4, 0x141a41000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+
+    /* MPAM_MSC_NODE 5 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x5, 0x142601000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+
+    /* MPAM_MSC_NODE 6 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x6, 0x142641000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+
+    /* MPAM_MSC_NODE 7 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x7, 0x142a01000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+
+    /* MPAM_MSC_NODE 8 */
+    {
+      RD_MPAM_MSC_NODE_INIT(0x8, 0x142a41000, 0, MPAM_MSC_COUNT,
+        RESOURCES_PER_MSC, FUNCTIONAL_DEPENDENCY_PER_RESOURCE)
+    },
+  }
+};
+
+VOID* CONST ReferenceAcpiTable = &Mpam;

Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf

@@ -22,6 +22,7 @@
   RdN2Cfg1/Dsdt.asl
   RdN2Cfg1/Madt.aslc
   RdN2Cfg1/Mcfg.aslc
+  RdN2Cfg1/Mpam.aslc
   RdN2Cfg1/Pptt.aslc
   RdN2Cfg1/Ssdt.asl
   Spcr.aslc
@@ -61,6 +62,7 @@
   gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
   gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
   gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+  gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
   gArmSgiTokenSpaceGuid.PcdOscLpiEnable
   gArmSgiTokenSpaceGuid.PcdOscCppcEnable
   gArmSgiTokenSpaceGuid.PcdPciBusCountPerRb