Rohit Mathew authored Apr 14, 2022 and Omkar Kulkarni committed Sep 27, 2022

Add MPAM ACPI table based on MPAM ACPI 1.0 specification for RD-N2-Cfg1
reference design platform. OS would query this table to understand
about the type and details of the MSCs supported by the platform.

RD-N2-Cfg1 platform supports 8 SLC slices. Each of these slices have
individual MPAM MSC controls and register set. PPTT defines this group
of cache slices as one single cache, tagged with a unique cache ID. All
the MSCs would in-turn refer to this unique cache ID given in the PPTT
ACPI description.

As the macro SGI_REMOTE_CHIP_MEM_OFFSET is used by
RD_MPAM_MSC_NODE_INIT macro, add a reference to
PcdMaxAddressBitsPerChip PCD.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I8e5111b51225abae4ee8a896c3817c8bb88667a7